Static core

In integrated circuit design, static core generally refers to a microprocessor (MPU) entirely implemented in static logic.[1] A static core MPU may be halted by stopping the system clock oscillator that is driving it, maintaining its state and resume processing at the point where it was stopped when the clock signal is restarted, as long as power continues to be applied. Static core MPUs are fabricated in the CMOS process and hence consume very little power when the clock is stopped, making them useful in designs in which the MPU remains in standby mode until needed and minimal loading of the power source (often a battery) is desirable during standby.[2]

In comparison, dynamic core microprocessor designs, those without a static core, only refresh and present valid outputs on their pins during specific periods of the clock cycle. If the clock is slowed, or stopped, the charge on the pin leaks out of the capacitors over time, quickly moving to the default state and no longer being valid. Dynamic designs have to run within a set range of clock frequencies to avoid this problem.

Static core microprocessors include the RCA 1802, Intel 80386EX, WDC W65C02S, WDC W65C816S and Freescale 683XX family.

Many low-power electronics systems are designed as fully static systems—such as, for example, the Psion Organiser,[3] the TRS-80 Model 100, and the Galileo spacecraft. In such a fully static system, the processor has a static core and data is stored in static RAM, rather than dynamic RAM. Such design features allow the entire system to be "paused" indefinitely in a low power state, and then instantly resumed when needed.[3]

References

  1. ^ "Static core and Related Topics". hyperleapsite. Archived from the original on August 7, 2022. Retrieved 2022-08-07.
  2. ^ "Static core". Semantic Scholar. Retrieved 2022-08-07.
  3. ^ a b Richard Murray. "PocketBook II hardware".

See also


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