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A Flip Field-Effect Transistor (FFET) is a three-dimensional (3D) stacked transistor architecture where transistors are fabricated on both the frontside and the backside of a semiconductor wafer.^{[1] [2] [3]} These dual-sided transistors are then connected by dual-sided interconnects, enabling increased transistor density and potential improvements in power and performance for future integrated circuits. The architecture is named after the "flipping" process that allows for fabrication on both sides of the wafer. ^[4]. ^{[5] [6]}

Considering it integrates both N/P transistor, FFET is primarily an integration concept rather than a specific device type, meaning it can be implemented with various underlying transistor architectures such as planar devices, Fin field-effect transistor^{[7] [8]}, or nanosheet transistors. This flexibility allows for a symmetric design that offers unique advantages over other stacked architectures like the Complementary FET (CFET).^{[9] [10]}

A key benefit of FFET is its ability to enable highly compact standard cell designs, which can achieve a cell height of 2.5T (2 tracks) or less ^[1]. By distributing transistors and interconnects on both sides of the wafer, FFET provides more signal tracks and better routability. leading to a smaller cell area and more energy-efficient logic libraries compared to conventional stacked transistor technologies.

Since the FFET focuses on using both sides of wafer to do transistor stacking. The FFET fabrication process is distinct from conventional methods due to its dual-sided approach.

Frontside Fabrication: The process begins with the standard fabrication steps for the frontside of the wafer, including self-aligned active patterning and subsequent front-end-of-line (FEOL) and back-end-of-line (BEOL) processes. Wafer Flipping and Bonding: After the frontside is complete, the wafer is bonded to a carrier and then flipped. Backside Preparation: The original substrate is thinned down by grinding and chemical mechanical polishing (CMP) until the backside self-aligned active region is exposed.^[1] Backside Fabrication: The fabrication continues on the backside, largely following a conventional flow, but with specific modifications like gate merge (GM) and drain merge (DM) to create shared nodes between the frontside and backside transistors.

The separation of the frontside and backside fabrication flows results in lower aspect ratio requirements compared to monolithic CFETs,^[9] making FFET a more manufacturing-friendly process.

Different from typical standard cell in CMOS with connection pins on the frontside of wafer, FFET standard cells utilize a dual-sided design to optimize space and connectivity.

Gate and Drain Merge: Through middle-of-line (MOL) techniques, such as Gate Merge (GM) and Drain Merge (DM), complementary transistors on opposite sides of the wafer can share common nodes.^[11] Other techniques like Field Drain Merge (FDM) and Buried Signal Track (BST) are used to resolve alignment and congestion.^[11]

Dual-Sided Output Pins: FFET cells are designed with dual-sided output pins, accessible from both the frontside and backside simultaneously. This design choice enables flexible inter-cell connectivity and more efficient signal routing.^[11] While input pins are typically on a single side, they can be re-assigned during design optimization to balance flexibility with pin density.^[11]

Physical implementation of FFET leverages dual-sided routing, where nets on both sides are routed separately and then merged, allowing for efficient signal and power delivery even with reduced metal layer counts.^[12]

The principles of FFET can be extended into the Flip 3D (F3D) integration, which creates multi-layered 3D integrated circuits by repeatedly applying the wafer flipping and bonding process. ^[13] F3D aims to fully utilize both sides of the wafer for stacking logic and memory.

Key features of F3D include:

Dual-Sided I/O Connectivity: Advanced bonding schemes allow both the frontside and backside of a die to participate in hybrid bonding, enabling flexible stacking orientations and potentially eliminating the need for traditional through-silicon vias (TSVs).^[13]

Monolithic 3D Integration: F3D supports monolithic 3D integration on both sides of the wafer under a more relaxed thermal budget, expanding the design space for future 3D chip stacking and co-integration technologies.^[13]

FinFET

Multigate device

Moore's Law

Integrated circuit