Azuro, Inc. is an electronic design automation (EDA) software company. Formerly headquartered in Santa Clara, California with a development office in Cambridge, England, it is now part of Cadence Design Systems.

Azuro develops software for the design of integrated circuits. Azuro specializes in clock network implementation. Azuro's PowerCentric product takes an innovative approach to clock network implementation that produces lower power clock networks with lower clock skew and shorter insertion delay using a smaller area of the integrated circuit than competing tools.

Azuro has been particularly focussed on lower power design. In synchronous circuit designs all changes of state are coordinated by a clock, and this clock edge must be distributed to all parts of the chip. Since the clock signal is distributed throughout the entire circuit it can consume a large percentage of the energy used. Azuro's technology allows clock gating and clock network implementation to be combined as a single step, allowing the clock to be prevented from reaching parts of the chip where it is not needed more effectively than competing technologies. The company has a number of patents in the area of low power design, clock tree synthesis and power analysis.

Azuro was founded in Cambridge in 2002 by Paul Cunningham and Steev Wilcox, using research from their doctoral studies.^[1]

On July 12, 2011 Cadence Design Systems announced that it had acquired Azuro for an undisclosed sum.^[1][2]

• Electronic design automation
• Design flow (EDA)
• Integrated circuit design

• EETimes: Power reduction tool extends to 65-nm
• EETimes: Starc adopts Azuro's clock-tree synthesis.
• EDN: Azuro Cuts Power in 65nm Digital Designs
• EDN: Power-savvy tool replaces clock-tree synthesis
• EETimes Europe: Startup targets power problems in wireless IC design